Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications

conference digital integrated circuits elemental semiconductors flexible electronics grain boundaries integrated circuit design low-power electronics response surface methodology silicon thin film transistors si battery-operated portable electronics defect grain boundary region device-to-device variation flexible substrate low-cost digital design low-temperature polycrystalline silicon thin film transistors multifinger parallel structure power dissipation response surface method scaled ltps tft size 200 nm statistical variation variation-aware circuit design voltage 10 v to 20 v circuit synthesis digital circuits flexible printed circuits glass grain boundaries polymers silicon substrates temperature thin film transistors low-temperature polycrystalline-silicon (ltps) response surface method (rsm) grain boundary (gb) thin film transistor (tft)