Yiran Chen

Publications (2)

• Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance (2010). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (11), 1621–1624
• Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI (2007). 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug, 2007