Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

conference mosfet adders logic design low-power electronics nbti-induced delay degradation nbti-tolerant techniques vl-adder arithmetic circuit design clock edge energy efficiency lower-power adder designs manufacturing costs nanoscale pmos transistors negative bias temperature instability variable-latency adder technique adders arithmetic circuit synthesis clocks degradation delay mosfets negative bias temperature instability niobium compounds titanium compounds negative bias temperature instability (nbti) variable-latency adder (vl-adder)