| Penn Computational Intelligence Lab

Yue Zha

PhD Candidate

Department of Electrical and Systems Engineering

University of Pennsylvania

Yue Zha received his B.S. degree in Physics from Peking University in 2013, and M.S. degree in Electrical and Computer Engineering and Computer Science from University of Wisconsin-Madison in 2015. He is currently pursuing his Ph.D. degree at the Department of Electrical and Systems Engineering, University of Pennsylvania.

Interests

Reconfigurable architecture, including both CMOS-based and RRAM-based
Processing-In-Memory architecture for big-data
System and compilation support for novel computing architecture

Education

MS in Computer Engineering, 2015

University of Wisconsin-Madison
BS in Physics, 2013

Peking University, China

Publications (18)

When Application-Specific ISA Meets FPGAs: A Multi-LayerVirtualization Framework for Heterogeneous Cloud FPGAs (2021). the 25th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘21, March, 2021
Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization (2020). 2020 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ser. ISCA ‘20, forthcoming, 2020
ViTAL: Virtualizing FPGAs in the Cloud (2020). the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘20, March, 2020
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications (INVITED) (2020). IEEE Journal of Solid-State Circuits (JSSC), 55(4), 908-919, 2020
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications (2019). 2019 IEEE Symposium on VLSI Circuits, Jun, 2019
MEG: A RISCV-based system simulation infrastructure for exploring memory optimization using FPGAs and Hybrid Memory Cube (Best Paper Nominee) (2019). 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2019
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support (2018). 23nd International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘18, Williamsburg, VA, USA, Mar, 2018
Liquid Silicon: A Data-Centric Reconfigurable Architecture enabled by RRAM Technology (2018). Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018
Specialization: A New Path towards Low Power (INVITED) (2018). ASP Journal of Low Power Electronics, 2018, 14, (2)
An Alternative Analytical Approach to Associative Processing (Best of CAL) (2018). IEEE Computer Architecture Letters, 17, (2), 113-116
RRAM-based reconfigurable in-memory computing architecture with hybrid routing (2017). 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), ser. ICCAD ‘17, Nov, 2017
CMA: A Reconfigurable Complex Matching Accelerator for Wire-speed Network Intrusion Detection (2017). IEEE Computer Architecture Letters, 17, (1), 33-36
RRAM-based Reconfigurable In-Memory Computing Architecture with Hybrid Routing (poster) (2017). the 54th Annual Design Automation Conference Work-in-Progress, ser. DAC-WIP ‘17, Austin, TX, USA, Jun, 2017
Challenges and Opportunities: From Near-memory Computing to In-memory Computing (INVITED) (2017). Proceedings of the 2017 ACM on International Symposium on Physical Design, ser. ISPD ‘17, Portland, Oregon, USA, Mar, 2017
Recent progress in RRAM technology: From compact models to applications (INVITED) (2017). 2017 China Semiconductor Technology International Conference (CSTIC), March, 2017
A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by RRAM Technology (poster) (2017). Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar (2017). IEEE Computer Architecture Letters, 16, (2), 123–126
Reconfigurable in-memory computing with resistive memory crossbar (2016). Proceedings of the 35th International Conference on Computer-Aided Design, ser. ICCAD ‘16, Austin, Texas, 2016