1Mb 0.41 um^2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)

This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve 10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM …

A Novel Reconfigurable Sensing Scheme for Variable Level Storage in Phase Change Memory

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

(Acceptance Rate: underline39%, 74 out of 192)