Kaushik Roy

Publications (16)

• Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective (Best Paper) (2010). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (12), 1710–1723
• Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance (2010). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (11), 1621–1624
• Variation Resilient Spin Torque Transfer MRAM (poster) (2009). GSRC Workshop, Dallas, TX, USA, Mar, 2009
• An Alternate Design Paradigm for Robust Spin-torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective (2009). Proceedings of the 2009 Asia and South Pacific Design Automation Conference, ser. ASP-DAC ‘09, Yokohama, Japan, Jan, 2009
• Robust Heterogeneous System Design in Spintronics: Error Resilient Spin Torque MRAM (STT MRAM) Design (2009). the 46th Annual Design Automation Conference PHD Forum, ser. DAC ‘09, 2009
• Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications (2009). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, (1), 46–59
• Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement (2008). 2008 IEEE Custom Integrated Circuits Conference (CICC), Sept, 2008
• An Alternate Design Paradigm for Low-power, Low-cost, Testable Hybrid Systems Using Scaled LTPS TFTs (INVITED) (2008). J. Emerg. Technol. Comput. Syst., 4, (3), 13:1–13:19
• Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement (2008). 2008 45th ACM/IEEE Design Automation Conference (DAC), June, 2008
• Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic RAM (STT MRAM) Array for Yield Enhancement (2008). SRC Technology and Talent for the 21st Century Technology (TECHCON), 2008
• Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation (2007). IEEE Transactions on Electron Devices, 54, (11), 2918-2929
• A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs (2007). 2007 IEEE International Test Conference (ITC), Oct, 2007
• High Performance and Low Power Electronics on Flexible Substrate (2007). 2007 44th ACM/IEEE Design Automation Conference (DAC), June, 2007
• Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications (2007). 2007 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), May, 2007
• Low Power and Variation Tolerant Digital Circuit Design in Sub-micron Regime using Low Cost LTPS TFTs (2007). SRC Technology and Talent for the 21st Century Technology (TECHCON), 2007
• Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation (2006). 2006 64th Device Research Conference (DRC), June, 2006