Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling

Xiaoxin Xu, Qing Luo, Tiancheng Gong, Hangbing Lv, Shibing Long, Qi Liu, Steve S. Chung, Jing Li, Ming Liu
DOI
Type
Conference paper
Publication
2016 IEEE Symposium on VLSI Technology, June, 2016
conference cmos memory circuits integrated circuit manufacture resistive ram cmos rram self-aligned self-selective cell size 5 nm vertical resistive switching memory etching hafnium compounds leakage currents programming resistance three-dimensional displays threshold voltage