Publications

We published in top-tier peer-reviewed conference proceedings and journal articles on various top-ics in computer area, ranging from IEDM, IRPS, VLSI Circuit and Technology Symp., DAC, ICCAD, to FPGA, FCCM, ASPLOS, CVPR, ICLR, etc. A full list is below.

(2020). Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization. 2020 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ser. ISCA ‘20, forthcoming, 2020.

Project

(2020). ViTAL: Virtualizing FPGAs in the Cloud. the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘20, March, 2020.

Project Video DOI

(2019). Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization (Poster). the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘19, Feb, 2019.

DOI

(2018). Efficient Large-scale Approximate Nearest Neighbor Search on the OpenCL-FPGA. Conference on Computer Vision and Pattern Recognition (CVPR), Jun, 2018.

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(2018). PQ-CNN: Accelerating Product Quantized Convolutional Neural Network (Poster). 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2018.

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(2018). Adaptive Quantization of Neural Networks. International Conference on Learning Representations (ICLR), April, 2018.

(2018). Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support. 23nd International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘18, Williamsburg, VA, USA, Mar, 2018.

Project DOI

(2018). Nonvolatile Memory Outlook: Technology Driven or Application Driven? (INVITED). 2018 China Semiconductor Technology International Conference (CSTIC), March, 2018.

(2018). Liquid Silicon: A Data-Centric Reconfigurable Architecture enabled by RRAM Technology. Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018.

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(2018). Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform. Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018.

Project DOI

(2018). Accelerating Graph Analytics By Co-Optimizing Storage and Access on an FPGA-HMC Platform. Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018.

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(2018). Specialization: A New Path towards Low Power (INVITED). ASP Journal of Low Power Electronics, 2018, 14, (2).

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(2017). RRAM-based reconfigurable in-memory computing architecture with hybrid routing. 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), ser. ICCAD ‘17, Nov, 2017.

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(2017). RRAM-based Reconfigurable In-Memory Computing Architecture with Hybrid Routing (poster). the 54th Annual Design Automation Conference Work-in-Progress, ser. DAC-WIP ‘17, Austin, TX, USA, Jun, 2017.

(2017). Accelerating Large-Scale Graph Analytics with FPGA and HMC (Poster). 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2017.

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(2017). Challenges and Opportunities: From Near-memory Computing to In-memory Computing (INVITED). Proceedings of the 2017 ACM on International Symposium on Physical Design, ser. ISPD ‘17, Portland, Oregon, USA, Mar, 2017.

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(2017). Recent progress in RRAM technology: From compact models to applications (INVITED). 2017 China Semiconductor Technology International Conference (CSTIC), March, 2017.

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(2017). Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017.

Project DOI

(2017). IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar. IEEE Computer Architecture Letters, 16, (2), 123–126.

DOI

(2017). Boosting the Performance of FPGA-based Graph Processor Using Hybrid Memory Cube: A Case for Breadth First Search. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017.

Project DOI

(2017). A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by RRAM Technology (poster). Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017.

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(2016). Reconfigurable in-memory computing with resistive memory crossbar. Proceedings of the 35th International Conference on Computer-Aided Design, ser. ICCAD ‘16, Austin, Texas, 2016.

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(2016). A compact model for RRAM including random telegraph noise. 2016 IEEE International Reliability Physics Symposium (IRPS), April, 2016.

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(2015). Enabling phase-change memory for data-centric computing: Technology, circuitand system (INVITED). 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May, 2015.

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(2012). A case for small row buffers in non-volatile main memories. 2012 IEEE 30th International Conference on Computer Design (ICCD), Sept, 2012.

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(2012). Resistance drift in phase change memory (INVITED). 2012 IEEE International Reliability Physics Symposium (IRPS), April, 2012.

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(2011). Materials engineering for Phase Change Random Access Memory. 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding (NVMTS), Nov, 2011.

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(2011). A non-volatile look-up table design using PCM (phase-change memory) cells. 2011 Symposium on VLSI Circuits - Digest of Technical Papers, June, 2011.

(2011). Phase change memory (INVITED). Science China Information Sciences, 54, (5), 1061–1072.

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(2010). Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (11), 1621–1624.

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(2009). Variation Resilient Spin Torque Transfer MRAM (poster). GSRC Workshop, Dallas, TX, USA, Mar, 2009.

(2009). An Alternate Design Paradigm for Robust Spin-torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective. Proceedings of the 2009 Asia and South Pacific Design Automation Conference, ser. ASP-DAC ‘09, Yokohama, Japan, Jan, 2009.

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(2009). Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, (1), 46–59.

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(2009). Robust Heterogeneous System Design in Spintronics: Error Resilient Spin Torque MRAM (STT MRAM) Design. the 46th Annual Design Automation Conference PHD Forum, ser. DAC ‘09, 2009.

(2008). Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. 2008 IEEE Custom Integrated Circuits Conference (CICC), Sept, 2008.

DOI

(2008). Body History Study on 12S eDRAM Sensing Operation. Semiconductor Research and Development Center (SRDC), IBM.

(2007). A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. 2007 IEEE International Test Conference (ITC), Oct, 2007.

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(2007). Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug, 2007.

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(2007). High Performance and Low Power Electronics on Flexible Substrate. 2007 44th ACM/IEEE Design Automation Conference (DAC), June, 2007.

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(2007). Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications. 2007 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), May, 2007.

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(2007). Low Power and Variation Tolerant Digital Circuit Design in Sub-micron Regime using Low Cost LTPS TFTs. SRC Technology and Talent for the 21st Century Technology (TECHCON), 2007.