| Penn Computational Intelligence Lab

Jing Li

Eduardo D. Glandt Faculty Fellow and Associate Professor

Department of Electrical and System Engineering

Department of Computer and Information Science

University of Pennsylvania

Dr. Jing (Jane) Li is the Eduardo D. Glandt Faculty Fellow and Associate Professor (with tenure) at the Department of Electrical and System Engineering and the Department of Computer and Information Science at the University of Pennsylvania. Previously she was the Dugald C. Jackson Assistant Professor at the University of Wisconsin–Madison and a faculty affiliate with the UW-Madison Computer Architecture group and Machine Learning group. She is one of the PIs in SRC JUMP center – Center for Research on Intelligent Storage and Processing-In-Memory (CRISP). She spent her early career at IBM T. J. Watson Research Center as a Research Staff Member after obtaining her PhD degree from Purdue University in 2009.

She is attracted to all the big problems she can find in computer system across the stack regardless the specific sub-areas. She is a passionate computer experimentalist and enjoy building real computer systems (both hardware and software). She has made contributions to the following “memory-centric” areas: 1) domain-specific accelerator and its interaction with emerging memories (HMC/HBM/NVM), 2) programmable in-memory computing architecture enabled by emerging nonvolatile memories (PCM/RRAM), 3) system support (e.g., virtualization) for accelerators (e.g., FPGA), and 4) FPGA-based full system simulation infrastructure (MEG) for memory system research. She has strong ties with leading technology companies and has successful technology transfer experience (>40 issued/pending patents).

She is the recipient of prestigious NSF Career Award in 2018, DARPA’s Young Faculty Award (one out of 2 in computer area and one out of 26 across all areas in science and technology nationwide, the first awardee in computer engineering and computer science at UW-Madison) in 2016, WARF Innovation Awards (WIA) Finalist (only 6 patented technologies out of 400+ patents got selected university wide), IBM Research Division Outstanding Technical Achievement Award in 2012 for successfully achieving CEO milestone, multiple invention achievement awards and high value patent application awards from IBM from 2010-2014, IBM Ph.D. Fellowship Award in 2008, Meissner Fellowship in 2004 from Purdue University, etc. Her research was reported by Yahoo News, Newegg Business, Digital Trends, etc. And she was featured in Madison Magazine (Channel 3000) as a rising research star.

She has been serving on the technical committee for the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), International Symposium on Computer Architecture (ISCA) (both regular and industry tracks), Machine Learning and Systems (MLSys), International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), International Symposium on High Performance Computer Architecture (HPCA), International Symposium on Field-Programmable Gate Arrays (FPGA), International Symposium on Field-Programmable Custom Computing Machines (FCCM), Design Automation Conference (DAC), International Conference on Computer‑Aided Design (ICCAD), IEEE Custom Integrated Circuits Conference (CICC), International Symposium on Low Power Electronics and Design (ISLPED), International Symposium on Microarchitecture (MICRO) (external), IEEE International Symposium on Circuits and Systems (ISCAS), International Electron Devices Meeting (IEDM), etc.. She served as the advisory chair/general chair / technical chair / finance chair / publicity chair for a premier industry memory conference – International Memory Workshop (IMW) and co-organized it with Intel/Micron/SK Hynix/CEA LETI to hold annual meetings with worldwide memory vendors. She is in the Steering/Organizing Committee for IMW, and serves as the Publicity Chair for FPGA’20, FPGA’19 and ISLPED’18, the Demo Chair for MLSys’20, the Best Paper committee Co-Chair for TRETS. She serves as Best Paper committee for several conferences including FCCM and CICC. She is an editor for Journal of Low Power Electronics (JOLPE), and associate editor for Transactions on Reconfigurable Technology and System (TRETS) and IEEE Computer Architecture Letters (CAL). She is serving at ACM SIGDA Technical Committee on FPGAs and Reconfigurable Computing (TC-FPGA).

Interests

Computer Architecture
Compiler
Distributed Systems
VLSI
Machine Learning

Education

PhD in Computer Engineering, 2009

Purdue University
BSc in Electrical Engineering, 2004

Shanghai Jiaotong University

Publications (75)

When Application-Specific ISA Meets FPGAs: A Multi-LayerVirtualization Framework for Heterogeneous Cloud FPGAs (2021). the 25th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘21, March, 2021
Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization (2020). 2020 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ser. ISCA ‘20, forthcoming, 2020
ViTAL: Virtualizing FPGAs in the Cloud (2020). the 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘20, March, 2020
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications (INVITED) (2020). IEEE Journal of Solid-State Circuits (JSSC), 55(4), 908-919, 2020
Interleaved Composite Quantization for High-Dimensional Similarity Search (2019). arXiv preprint arXiv:1912.08756
TOCO: A Framework for Compressing Neural Network Models Based on Tolerance Analysis (2019). arXiv preprint arXiv:1912.08792
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications (2019). 2019 IEEE Symposium on VLSI Circuits, Jun, 2019
Nb(1-x)O2 based Universal Selector with Ultra-high Endurance (>10^12), high speed (10ns) and Excellent Vth Stability (2019). 2019 IEEE Symposium on VLSI Technology, Jun, 2019
MEG: A RISCV-based system simulation infrastructure for exploring memory optimization using FPGAs and Hybrid Memory Cube (Best Paper Nominee) (2019). 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2019
MLSys: The New Frontier of Machine Learning Systems (2019). arXiv preprint arXiv:1904.03257
Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization (Poster) (2019). the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘19, Feb, 2019
Efficient Large-scale Approximate Nearest Neighbor Search on the OpenCL-FPGA (2018). Conference on Computer Vision and Pattern Recognition (CVPR), Jun, 2018
PQ-CNN: Accelerating Product Quantized Convolutional Neural Network (Poster) (2018). 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2018
Adaptive Quantization of Neural Networks (2018). International Conference on Learning Representations (ICLR), April, 2018
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support (2018). 23nd International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ‘18, Williamsburg, VA, USA, Mar, 2018
Nonvolatile Memory Outlook: Technology Driven or Application Driven? (INVITED) (2018). 2018 China Semiconductor Technology International Conference (CSTIC), March, 2018
Accelerating Graph Analytics By Co-Optimizing Storage and Access on an FPGA-HMC Platform (2018). Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform (2018). Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018
Liquid Silicon: A Data-Centric Reconfigurable Architecture enabled by RRAM Technology (2018). Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘18, Monterey, California, USA, Feb, 2018
Specialization: A New Path towards Low Power (INVITED) (2018). ASP Journal of Low Power Electronics, 2018, 14, (2)
Computing Generalized Matrix Inverse on Spiking Neural Substrate (2018). Frontiers in neuroscience: Neuromorphic engineering, 12, 115
An Alternative Analytical Approach to Associative Processing (Best of CAL) (2018). IEEE Computer Architecture Letters, 17, (2), 113-116
RRAM-based reconfigurable in-memory computing architecture with hybrid routing (2017). 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), ser. ICCAD ‘17, Nov, 2017
CMA: A Reconfigurable Complex Matching Accelerator for Wire-speed Network Intrusion Detection (2017). IEEE Computer Architecture Letters, 17, (1), 33-36
RRAM-based Reconfigurable In-Memory Computing Architecture with Hybrid Routing (poster) (2017). the 54th Annual Design Automation Conference Work-in-Progress, ser. DAC-WIP ‘17, Austin, TX, USA, Jun, 2017
Accelerating Large-Scale Graph Analytics with FPGA and HMC (Poster) (2017). 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April, 2017
Challenges and Opportunities: From Near-memory Computing to In-memory Computing (INVITED) (2017). Proceedings of the 2017 ACM on International Symposium on Physical Design, ser. ISPD ‘17, Portland, Oregon, USA, Mar, 2017
Recent progress in RRAM technology: From compact models to applications (INVITED) (2017). 2017 China Semiconductor Technology International Conference (CSTIC), March, 2017
A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by RRAM Technology (poster) (2017). Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017
Boosting the Performance of FPGA-based Graph Processor Using Hybrid Memory Cube: A Case for Breadth First Search (2017). Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar (2017). IEEE Computer Architecture Letters, 16, (2), 123–126
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network (2017). Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ser. FPGA ‘17, Monterey, California, USA, 2017
Reconfigurable in-memory computing with resistive memory crossbar (2016). Proceedings of the 35th International Conference on Computer-Aided Design, ser. ICCAD ‘16, Austin, Texas, 2016
Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling (2016). 2016 IEEE Symposium on VLSI Technology, June, 2016
A compact model for RRAM including random telegraph noise (2016). 2016 IEEE International Reliability Physics Symposium (IRPS), April, 2016
Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells (2015). 2015 IEEE International Electron Devices Meeting (IEDM), Dec, 2015
Enabling phase-change memory for data-centric computing: Technology, circuitand system (INVITED) (2015). 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May, 2015
1 Mb 0.41 um^2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (INVITED) (2014). IEEE Journal of Solid-State Circuits, 49, (4), 896–907
1Mb 0.41 um^2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year) (2013). 2013 Symposium on VLSI Circuits, June, 2013
Assisted cubic to hexagonal phase transition in GeSbTe thin films on silicon nitride (2013). Thin Solid Films, 536, 216–219
Evaluating Row Buffer Locality in Future Non-Volatile Main Memories (2012). Carnegie Mellon University (CMU)
Theory and Experiments of the Impact of Work-Function Variability on Threshold Voltage Variability in MOS Devices (2012). IEEE Transactions on Electron Devices, 59, (11), 3124–3126
A case for small row buffers in non-volatile main memories (2012). 2012 IEEE 30th International Conference on Computer Design (ICCD), Sept, 2012
The impact of heater-recess and load matching in phase change memory mushroom cells (2012). Nanotechnology, 23, (22), 225201
Optimization of programming current on endurance of phase change memory (2012). Proceedings of Technical Program of 2012 VLSI Technology, System and Application (VLSI-TSA), April, 2012
Resistance drift in phase change memory (INVITED) (2012). 2012 IEEE International Reliability Physics Symposium (IRPS), April, 2012
The impact of melting during reset operation on the reliability of phase change memory (2012). 2012 IEEE International Reliability Physics Symposium (IRPS), April, 2012
A low power phase change memory using thermally confined TaN/TiN bottom electrode (2011). 2011 International Electron Devices Meeting (IEDM), Dec, 2011
Explore physical origins of resistance drift in phase change memory and its implication for drift-insensitive materials (2011). 2011 International Electron Devices Meeting (IEDM), Dec, 2011
Materials engineering for Phase Change Random Access Memory (2011). 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding (NVMTS), Nov, 2011
Post-silicon calibration of analog CMOS using phase-change memory cells (2011). 2011 Proceedings of the ESSCIRC (ESSCIRC), Sept, 2011
A non-volatile look-up table design using PCM (phase-change memory) cells (2011). 2011 Symposium on VLSI Circuits - Digest of Technical Papers, June, 2011
A Novel Reconfigurable Sensing Scheme for Variable Level Storage in Phase Change Memory (2011). 2011 3rd IEEE International Memory Workshop (IMW), May, 2011
Demonstration of CAM and TCAM Using Phase Change Devices (2011). 2011 3rd IEEE International Memory Workshop (IMW), May, 2011
Phase change memory (INVITED) (2011). Science China Information Sciences, 54, (5), 1061–1072
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective (Best Paper) (2010). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (12), 1710–1723
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance (2010). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, (11), 1621–1624
Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability (2009). 2009 IEEE International Electron Devices Meeting (IEDM), Dec, 2009
Variation Resilient Spin Torque Transfer MRAM (poster) (2009). GSRC Workshop, Dallas, TX, USA, Mar, 2009
An Alternate Design Paradigm for Robust Spin-torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective (2009). Proceedings of the 2009 Asia and South Pacific Design Automation Conference, ser. ASP-DAC ‘09, Yokohama, Japan, Jan, 2009
Robust and Energy-efficient Heterogeneous System Design in Emerging Technologies (**Best Thesis Award nominee**) (2009). Electrical and Computer Engineering
Robust Heterogeneous System Design in Spintronics: Error Resilient Spin Torque MRAM (STT MRAM) Design (2009). the 46th Annual Design Automation Conference PHD Forum, ser. DAC ‘09, 2009
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications (2009). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, (1), 46–59
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement (2008). 2008 IEEE Custom Integrated Circuits Conference (CICC), Sept, 2008
An Alternate Design Paradigm for Low-power, Low-cost, Testable Hybrid Systems Using Scaled LTPS TFTs (INVITED) (2008). J. Emerg. Technol. Comput. Syst., 4, (3), 13:1–13:19
Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement (2008). 2008 45th ACM/IEEE Design Automation Conference (DAC), June, 2008
Body History Study on 12S eDRAM Sensing Operation (2008). Semiconductor Research and Development Center (SRDC), IBM
Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic RAM (STT MRAM) Array for Yield Enhancement (2008). SRC Technology and Talent for the 21st Century Technology (TECHCON), 2008
Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital Operation (2007). IEEE Transactions on Electron Devices, 54, (11), 2918-2929
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs (2007). 2007 IEEE International Test Conference (ITC), Oct, 2007
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI (2007). 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug, 2007
High Performance and Low Power Electronics on Flexible Substrate (2007). 2007 44th ACM/IEEE Design Automation Conference (DAC), June, 2007
Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications (2007). 2007 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), May, 2007
Low Power and Variation Tolerant Digital Circuit Design in Sub-micron Regime using Low Cost LTPS TFTs (2007). SRC Technology and Talent for the 21st Century Technology (TECHCON), 2007
Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation (2006). 2006 64th Device Research Conference (DRC), June, 2006

Talks

Liquid Silicon: A 10-year Journey Towards New Computing Paradigm, Dept. of Electrical Engineering, Stanford University, Apr. 4, 2019
Liquid Silicon: A New Computing Paradigm Enabled by Monolithic 3D Cross-point Memory, Dept. of Computer Science, University of Chicago, Nov. 11, 2018
Liquid Silicon: A New Computing Paradigm Enabled by Monolithic 3D Cross-point Memory, Dept. of Electrical and Computer Engineering, University of California, Los Angeles (UCLA), Oct. 10, 2018