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Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance
Yiran Chen
,
Hai Li
,
Cheng-Kok Koh
,
Guangyu Sun
,
Jing Li
,
Yuan Xie
,
Kaushik Roy
November 2010
Cite
DOI
Type
Journal article
Publication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
,
18
, (11), 1621–1624
journal
adders
digital arithmetic
integrated circuit design
logic design
ic design
nbti tolerance
circuit delay
digital arithmetic
logic design
negative bias temperature instability
variable-latency adder designs
word length 64 bit
adders
circuits
clocks
delay
negative bias temperature instability
niobium compounds
sun
throughput
titanium compounds
very large scale integration
digital arithmetic
ic design
logic design
Cite
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