1 Mb 0.41 um^2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (INVITED)

Jing Li, Robert Montoye, Masatoshi Ishii, Leland Chang
DOI

Abstract

This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90 nm CMOS technology and mushroom phase-change memory (PCM) technology. The primary challenge for enabling reliable array operation with such aggressive cell is presented, namely, severely degraded sensing margin due to significantly lower ON/OFF ratio of resistive memories (~10^2 for PCM) than that of traditional MOSFETs (>10^5 ). To address this challenge, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding and 2) a clocked self-referenced sensing scheme (CSRSS). In addition, the two-bit encoding can also improve algorithmic mapping by effectively compressing TCAM entries. The 1 Mb chip demonstrates reliable low voltage search operation (VDDmin ~750 mV) and a match delay of 1.9 ns under nominal operating conditions.

Type
Journal article
Publication
IEEE Journal of Solid-State Circuits, 49, (4), 896–907
journal content-addressable storage encoding phase change memories 2t 2r cell nonvolatile tcam cmos technology algorithmic mapping clocked self referenced sensing phase change memory technology resistive memories size 90 nm time 1.9 ns two bit encoding arrays encoding microprocessors phase change materials random access memory sensors associative computing encoding hardware accelerator intrusion detection matchline compensation nonvolatile packet classification phase change memory (pcm) search engine self-referenced sensing ternary content addressable memory (tcam)
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Jing Li
Eduardo D. Glandt Faculty Fellow and Associate Professor

Attracted to all the big problems in computer system across the stack regardless the specific sub-areas.