1Mb 0.41 um^2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing (Highlight Paper of the Year)

Jing Li, Robert Montoye, Masatoshi Ishii, Kevin Stawiasz, Takeshi Nishida, Kim Maloney, Gary Ditlow, Scott Lewis, Tom Maffitt, Richard Jordan, others

Abstract

This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.

Type
Conference paper
Publication
2013 Symposium on VLSI Circuits, June, 2013

(Acceptance Rate: underline27%, 109 out of 396)

conference cmos memory circuits sram chips clocks content-addressable storage integrated circuit design integrated circuit reliability low-power electronics phase change memories search problems 2-transistor-2-resistive-storage cells 2t-2r cells csrss ibm cmos technology pcm process sram-based tcam bit rate 1 mbit/s cell nonvolatile tcam cell size clocked self-referenced sensing scheme compact cells fabricated nonvolatile tcam low voltage search operation match delay mushroom phase-change memory process reliable search operation size 90 nm technology node test chip design two-bit encoding arrays clocks encoding microprocessors phase change materials sensors
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Jing Li
Eduardo D. Glandt Faculty Fellow and Associate Professor, Co-director for CyberSavvy Center

Attracted to all the big problems in computer system across the stack regardless the specific sub-areas.